The present invention pertains to communication between a microprocessor controller and a plurality of subsystem peripheral and more particularly to a common arrangement for facilitating the transfer of data between the microprocessor and non-compatible peripheral subsystems.
In communication system design, it is necessary for a microprocessor to have the capability of addressing a number of independent subsystems. To achieve this end, subsystems are tied to the data and address buses of the microprocessor. The microprocessor may then address each individual subsystem to transfer data between the microprocessor and subsystem. Each subsystem must recognize its own address, so that only one subsystem responds when a particular address is output by the microprocessor.
Previously, unique addressing was provided by setting dual in line package (DIP) switches to a unique value for each subsystem. When an address was output by the microprocessor, the subsystem logic would decode that address and compare it with the address of the DIP switches in order to enable the subsystem to gain control of the microprocessor's buses. Only one subsystem would contain switches set to each address. Therefore, only the subsystem containing the particular address transmitted by the microprocessor would respond and be enabled on to the microprocessor's buses.
Another method of achieving this unique addressing was to provide strapping options on the backplane of each frame or file of printed wiring cards associated with a particular subsystem. These strapping options would then be wired to sources of logic 0 or logic 1 corresponding to a particular address. When an address was output by the microprocessor, each subsystem would then compare that address with respect to its fixed unique address and respond as outlined above.
The strapping options and DIP switches techniques produce electrical noise, which disrupts the circuit operation. As a result, these options are not reliable. In particular, the DIP switches are fragile and susceptible to breakage.
In addition, subsystem/microprocessor bus architectures are typically dependant upon one common power supply. Subsystems need the ability to be powered down individually without impacting the microprocessor's bus structure.
Lastly, subsystems are typically designed to be directly compatible with the logic inputs and outputs of a microprocessor. Microprocessor bus control units do not typically compensate for the difference in logic levels between microprocessors and their associated peripheral subsystems.